In some systems analog data samples are converted to digital numbers which are quantized in steps of the quantization interval q. A number n of successive samples are then summed. The sum may then be divided by n to obtain the average. If all the n samples lie between mq and (m+1) q, m being an integer other than o the average will be seen as (m + 1/2) q. Thus there may be an error in the average as great as q/2. The present invention reduces the error in the sample average to q/2 n by adding an improvement signal to the analog data.
It is noted that the conventional signal processor consists of a source of analog data, an analog to digital (A/D) converter, a clock, a summing circuit and a divider. The analog data is converted to a digital signal at intervals determined by the clock. The summing circuit summed n successive digital signals, then the divider divided the sum by n and produced the output signal. The invention introduces a clock controlled improvement signal to the analog signal to reduce the error in the sample average to q/2 n.